CYDC256B16 Datasheet, PDF (19/26 Pages) Cypress Semiconductor – 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Switching Waveforms (continued)
Write Cycle No.1: R/W Controlled Timing^{[41, 42, 43, 44, 45, 46]}
t_WC
ADDRESS
OE
[45, 46]
CE
R/W
DATA OUT
DATA IN
t_AW
t_SA
t_PWE^[44]
NOTE 48
t_HZWE^[47]
t_SD
t_HZOE^[47]
t_HA
t_LZWE
t_HD
NOTE 48
Write Cycle No. 2: CE Controlled Timing^{[41, 42, 43, 48]}
ADDRESS
[45, 46]
CE
t_SA
R/W
DATA IN
t_WC
t_AW
t_SCE
t_SD
t_HA
t_HD
Notes:
43. t_HA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
44. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t_PWE or (t_HZWE + t_SD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required t_SD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t_PWE.
45. To access RAM, CE = V_IL, SEM = V_IH.
46. To access upper byte, CE = V_IL, UB = V_IL, SEM = V_IH.
To access lower byte, CE = V_IL, LB = V_IL, SEM = V_IH.
47. Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
48. During this period, the I/O pins are in the output state, and input signals must not be applied.
Document #: 001-01638 Rev. *E
Page 19 of 26
[+] Feedback