CY8C20111_12 Datasheet, PDF (19/44 Pages) Cypress Semiconductor – CapSense® Express™ – One Button and Two Button Capacitive Controllers

CY8C20111, CY8C20121
CS_FILTERING
CapSense Filtering Register
CS_FILTERING: 56h
1/2 Button
7
6
5
4
3
2
1
0
Access: FD
RW: 0
RW: 1
RW: 0
RW: 00
Bit Name
RstBl
I2C_DS
Avg_En
Avg_Order[1:0]
This register provides an option for forced baseline reset and to enable and configure two different types of software filters.
Bit
Name
7
RstBl
5
I2C_DS
4
Avg_En
[1:0]
Avg_Order[1:0]
Description
This bit resets all the baselines and it is auto cleared to ‘0’.
0 All Baselines are not reset
1 All baselines are reset
When this bit is set to ‘1’ the CapSense scan sample is dropped if I²C
communication was active during scanning.
0 Disable the I²C drop sample filer
1 Enable the I²C drop sample filter
This bit enables average filter on raw counts.
0 Disable the average filter
1 Enable the average filter
These bits are used to select the number of CapSense samples to
average:
Avg_Order[1:0] in Hex
00
01
10
11
Samples to Average
2
4
8
16
CS_SCAN_POS_x
Scan Position Registers
CS_SCAN_POS_0: 5Ch
(Writable only in Setup mode)
1/2 Button
7
6
5
4
3
2
1
0
Access: FD
RW: 0
Bit Name
Scan_Pstn
CS_SCAN_POS_1: 5Dh (Not available for 1 Button)
(Writable only in Setup mode)
2 Button
7
6
5
4
3
2
1
0
Access: FD
RW: 1
Bit Name
Scan_Pstn
This register is used to set the position of the sensors in the switch table for proper scanning sequence because the CapSense sensors
are scanned in sequence.
This register should be set after setting 0x07, 0x50, and 0x51 registers.
Bit
Name
0
Scan_Pstn
Description
This bit sets the scan position.
Document Number: 001-53516 Rev. *H
Page 19 of 44