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CY7C1481V33_07 Datasheet, PDF (19/30 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Electrical Characteristics
Over the Operating Range[13, 14]
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
VDD
0°C to +70°C 3.3V –5%/+10%
–40°C to +85°C
VDDQ
2.5V – 5%
to VDD
Parameter
Description
Test Conditions
VDD
VDDQ
Power Supply Voltage
IO Supply Voltage
For 3.3V I/O
For 2.5V I/O
VOH
Output HIGH Voltage For 3.3V I/O, IOH = –4.0 mA
For 2.5V I/O, IOH = –1.0 mA
VOL
Output LOW Voltage For 3.3V I/O, IOL = 8.0 mA
For 2.5V I/O, IOL = 1.0 mA
VIH
Input HIGH Voltage[13] For 3.3V I/O
For 2.5V I/O
VIL
Input LOW Voltage[13] For 3.3V I/O
For 2.5V I/O
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
Except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
IDD
VDD Operating Supply VDD = Max, IOUT = 0 mA,
7.5-ns cycle, 133 MHz
Current
f = fMAX = 1/tCYC
10-ns cycle, 100 MHz
ISB1
Automatic CE
Max VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Power Down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
10-ns cycle, 100 MHz
ISB2
Automatic CE
Max VDD, Device Deselected, All speeds
Power Down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
ISB3
Automatic CE
Max VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Power Down
Current—CMOS Inputs
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
10-ns cycle, 100 MHz
ISB4
Automatic CE
Max VDD, Device Deselected, All Speeds
Power Down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—TTL Inputs f = 0, inputs static
Min
3.135
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
–30
–5
–5
Max Unit
3.6
V
VDD
V
2.625
V
V
V
0.4
V
0.4
V
VDD + 0.3V V
VDD + 0.3V V
0.8
V
0.7
V
5
µA
µA
5
µA
µA
30
µA
5
µA
335
mA
305
mA
200
mA
200
mA
150
mA
200
mA
200
mA
165
mA
Notes
13. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).
14. TPower-up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05284 Rev. *H
Page 19 of 30
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