CY7C1425KV18_12 Datasheet, PDF (19/33 Pages) Cypress Semiconductor – 36-Mbit QDR® II SRAM Two-Word Burst Architecture

CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Identification Register Definitions
Instruction Field
Revision number (31:29)
Cypress device ID (28:12)
CY7C1425KV18
000
11010011010001111
Cypress JEDEC ID (11:1)
00000110100
ID register presence (0)
1
Value
CY7C1412KV18
000
11010011010010111
00000110100
1
CY7C1414KV18
000
11010011010100111
00000110100
1
Description
Version number.
Defines the type of
SRAM.
Allows unique
identification of SRAM
vendor.
Indicates the presence
of an ID register.
Scan Register Sizes
Instruction
Bypass
ID
Boundary scan
Register Name
Bit Size
3
1
32
109
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
SAMPLE Z
010
RESERVED
011
SAMPLE/PRELOAD
100
RESERVED
101
RESERVED
110
BYPASS
111
Description
Captures the input and output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-57825 Rev. *G
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