CY7C1381CV25 Datasheet, PDF (19/35 Pages) Cypress Semiconductor – 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

CY7C1381CV25
CY7C1383CV25
2.5V TAP AC Test Conditions
Input pulse levels ...... ........................................VSS to 2.5V
Input rise and fall time...................................................... 1ns
Input timing reference levels .........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
1.25V
TDO
Z_O= 50Ω
50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 2.5V ±0.125V unless otherwise noted)^[11]
PARAMETER DESCRIPTION
TEST CONDITIONS
V_OH1
Output HIGH Voltage I_OH = -1.0 mA, V_DDQ = 2.5V
V_OH2
Output HIGH Voltage I_OH = -100 µA,V_DDQ = 2.5V
V_OL1
Output LOW Voltage I_OL = 8.0 mA, V_DDQ = 2.5V
V_OL2
Output LOW Voltage I_OL = 100 µA
V_DDQ = 2.5V
V_IH
Input HIGH Voltage
V_DDQ = 2.5V
V_IL
Input LOW Voltage
V_DDQ = 2.5V
I_X
Input Load Current GND < V_IN < V_DDQ
Note:
11. All voltages referenced to VSS (GND).
MIN
MAX
UNITS
2.0
V
2.1
V
0.4
V
0.2
V
1.7
V_DD + 0.3
V
-0.3
0.7
V
-5
5
µA
Identification Register Definitions
INSTRUCTION FIELD
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
CY7C1381CV25
(512KX36)
010
01011
000001
100101
00000110100
ID Register Presence Indicator (0)
1
CY7C1383CV25
(1MX18)
010
01011
000001
010101
00000110100
1
DESCRIPTION
Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
Scan Register Sizes
REGISTER NAME
Instruction
Bypass
Bypass
ID
Boundary Scan Order
BIT SIZE(X36)
3
1
32
72
BIT SIZE(X18)
3
1
32
72
Document #: 38-05241 Rev. *B
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