CY7C1354BV25 Datasheet, PDF (19/27 Pages) Cypress Semiconductor – 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture

CY7C1354BV25
CY7C1356BV25
AC Test Loads and Waveforms
OUTPUT
Z₀ = 50Ω
R_L = 50Ω
2.5V
Output
5 pF
V_L = 1.25V
(a)
INCLUDING
JIG AND
SCOPE
R=1667Ω
ALL INPUT PULSES^[16]
V_DD
90%
10%
0V
R = 1538Ω
< 1.0 ns
1.25V
90%
10%
< 1.0 ns
(b)
(c)
Thermal Resistance^[16]
Parameters
Description
Q_JA
Thermal Resistance
(Junction to Ambient)
Q_JC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
BGA Typ.
25
6
fBGA Typ. TQFP Typ.
27
25
6
9
Unit Notes
°C/W 17
°C/W 17
Switching Characteristics Over the Operating Range ^{[ 21, 22]}
-225
-200
-166
Parameter
t_Power[17]
Clock
Description
V_CC (typical) to the first access read or write
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
Unit
ms
t_CYC
Clock Cycle Time
F_MAX
Maximum Operating Frequency
t_CH
Clock HIGH
t_CL
Clock LOW
Output Times
4.4
5
6
ns
225
200
166 MHz
1.8
2.0
2.4
ns
1.8
2.0
2.4
ns
t_CO
t_EOV
t_DOH
t_CHZ
t_CLZ
t_EOHZ
t_EOLZ
Set-up Times
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z^{[18, 19, 20]}
Clock to Low-Z^{[18, 19, 20]}
OE HIGH to Output High-Z^{[18, 19, 20]}
OE LOW to Output Low-Z^{[18, 19, 20]}
2.8
3.2
3.5
ns
2.8
3.2
3.5
ns
1.25
1.5
1.5
ns
1.25 2.8
1.5
3.2
1.5
3.5
ns
1.25
1.5
1.5
ns
2.8
3.2
3.5
ns
0
0
0
ns
t_AS
Address Set-up Before CLK Rise
1.4
1.5
1.5
ns
t_DS
Data Input Set-up Before CLK Rise
1.4
1.5
1.5
ns
t_CENS
CEN Set-up Before CLK Rise
1.4
1.5
1.5
ns
t_WES
WE, BW_x Set-up Before CLK Rise
1.4
1.5
1.5
ns
t_ALS
ADV/LD Set-up Before CLK Rise
1.4
1.5
1.5
ns
Shaded areas contain advance information.
Notes:
16. Tested initially and after any design or process changes that may affect these parameters.
17. This part has a voltage regulator internally; t_power is the time power needs to be supplied above V_DD minimum initially, before a Read or Write operation can be
initiated.
18. t_CHZ, t_CLZ, t_EOLZ, and t_EOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19. At any given voltage and temperature, t_EOHZ is less than t_EOLZ and t_CHZ is less than t_CLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when V_DDQ = 2.5V.
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05292 Rev. *E
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