CY7C1305AV25 Datasheet, PDF (19/21 Pages) Cypress Semiconductor – 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture

PRELIMINARY
CY7C1305AV25
CY7C1307AV25
Boundary Scan Order (continued)
Bit #
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Bump ID
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1J
2J
3K
3J
2K
1K
2L
3L
1M
Boundary Scan Order (continued)
Bit #
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Bump ID
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Document #: 38-05496 Rev. *A
Page 19 of 21
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