CY8C20X36A_12 Datasheet, PDF (18/47 Pages) Cypress Semiconductor – 1.8 V CapSense® Controller with SmartSense™ Auto-tuning

CY8C20X36A/46A/66A/96A/46AS/66AS
48-pin QFN (OCD)
The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD). Note that this part is only used for in-circuit debugging.
Table 10. Pin Definitions – CY8C20066A ^{[29, 30]}
Pin
No.
1^[31]
2
3
4
5
6
7
8
9
10
11
12
13
14^[31]
15^[31]
16
17
Digital
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
IOHR
IOHR
Analog Name
OCDOE
I
P2[7]
I
P2[5]
I
P2[3]
I
P2[1]
I
P4[3]
I
P4[1]
I
P3[7]
I
P3[5]
I
P3[3]
I
P3[1]
I
P1[7]
I
P1[5]
CCLK
HCLK
I
P1[3]
I
P1[1]
18
Power
V_SS
19
I/O
D+
20
I/O
D-
21
Power
V_DD
22
IOHR
I
P1[0]
Description
OCD mode direction pin
Crystal output (XOut)
Crystal input (XIn)
I²C SCL, SPI SS
I²C SDA, SPI MISO
OCD CPU clock output
OCD high speed clock output
SPI CLK.
ISSP CLK^[32], I²C SCL, SPI
MOSI
Ground connection
USB D+
USB D-
Supply voltage
ISSP DATA^[32], I²C SDA, SPI
CLK^[33]
Figure 11. CY8C20066A
OCDO
AI
,
XOAuI t,,
PE2[7]
P2[5]
1
2
3
AI , XIn , P2[3] 4
AI , P2[1] 5
AI , P4[3] 6
AI , P4[1] 7
AI , P3[7] ₈
AI , P3[5] 9
AI , P3[3] 10
AI , P3[1] ₁₁
AI , I2 C SCL, SPI SS, P1[7] ₁₂
QFN
(Top View)
36 P2[6] ,AI
35 P2[4] ,AI
34 P2[2] ,AI
33 P2[0] ,AI
32 P4[2] ,AI
31 P4[0] ,AI
30 P3[6] ,AI
29 P3[4] , AI
28 P3[2] ,AI
27 P3[0] , AI
26 XRES
25 _{P1[6] , AI}
23
IOHR
I
P1[2]
Pin
No.
Digital
Analog
Name
24
IOHR
I
P1[4]
Optional external clock input 37
IOH
(EXTCLK)
I
P0[0]
25
IOHR
I
P1[6]
38
IOH
I
P0[2]
26
Input
XRES
Active high external reset with 39
IOH
I
P0[4]
internal pull-down
27
I/O
I
P3[0]
40
IOH
I
P0[6]
28
I/O
I
P3[2]
29
I/O
I
P3[4]
30
I/O
I
P3[6]
41
42^[31]
43^[31]
Power
V_DD
OCDO
OCDE
31
I/O
I
P4[0]
44
IOH
I
P0[7]
32
I/O
I
P4[2]
45
IOH
I
P0[5]
33
I/O
I
P2[0]
46
IOH
I
P0[3]
34
I/O
I
P2[2]
35
I/O
I
P2[4]
47
Power
V_SS
48
IOH
I
P0[1]
36
I/O
I
P2[6]
CP
Power
V_SS
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Description
Supply voltage
OCD even data I/O
OCD odd data output
Integrating input
Ground connection
Center pad must be connected to
ground
Notes
29. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
30.
The center pad (CP) on the QFN
it must be electrically floated and
package must be
not connected to
connected to ground
any other signal.
(V_SS)
for
best
mechanical,
thermal,
and
electrical
performance.
If
not
connected
to
ground,
31. This pin (associated with OCD part only) is required for connecting the device to ICE-Cube In-Circuit Emulator for firmware debugging purpose. To know more about
the usage of ICE-Cube, refer to CY3215-DK PSoC^® IN-CIRCUIT EMULATOR KIT GUIDE.
32. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
33. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
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