CY7C9689A_11 Datasheet, PDF (18/54 Pages) Cypress Semiconductor – TAXI™-compatible HOTLink Transceiver

CY7C9689A
Z_LOAD is that load seen by the one output when it is sourcing and
sinking current. With a known load impedance and a desired
signal swing, it is possible to calculate the value of the associated
CURSETA or CURSETB resistor that sets this current.
Unused differential output drivers should be left open, and can
reduce their power dissipation by connecting their respective
CURSETx input to V_DD.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts an external clock at
the REFCLK input, and multiples that clock by 2.5, 5, or 10 (3, 6,
or 12 when BYTE8/10 is LOW and the encoder is disabled) to
generate a bit-rate clock for use by the transmit shifter. It also
provides a character-rate clock used by the Transmit Controller
state machine.
The clock multiplier PLL can accept a REFCLK input between
8 MHz and 40 MHz, however, this clock range is limited by the
operation mode of the CY7C9689A as selected by the SPDSEL
and RANGESEL inputs, and to a limited extent, by the BYTE8/10
and FIFOBYP signals. The operating serial signalling rate and
allowable range of REFCLK frequencies is listed in Table 3.
Transmit Control State Machine
The Transmit Control State Machine responds to multiple inputs
to control the data stream passed to the encoder. It operates in
response to:
Table 3. Speed Select and Range Select Settings
SPDSEL
RANGESEL
Serial
Data Rate
(MBaud)
REFCLK^[7]
Frequency
(MHz)
LOW
LOW
LOW
HIGH^[6]
50–100
50–100
10–20
20–40
HIGH
LOW
100–200
10–20
HIGH
HIGH
100–200
20–40
■the state of the FIFOBYP input
■the presence of data in the Transmit FIFO
■the contents of the Transmit FIFO
■the state of the transmitter BIST enable (TXBISTEN)
■the state of external halt signal (TXHALT).
These signals are used by the Transmit Control State Machine
to control the data formatter, read access to the Transmit FIFO
and BIST. They determine the content of the characters passed
to the Encoder and Transmit Shifter.
When the Transmit FIFO is bypassed, the Transmit Control State
Machine operates synchronous to REFCLK. In this mode, data
from the TXDATA bus is passed directly from the Input Register
to the Pipeline Register. If no data is enabled into the Input
register (TXEN is deasserted or TXFULL is asserted) then the
Transmit Control State Machine presents a JK or LM (when
BYTE8/10 = LOW) Command Character code to the Encoder to
maintain link synchronization.
If both the Encoder and Transmit FIFO are bypassed and no data
is enabled into the Input Register, the Transmit Control State
Machine injects JK or LM (when BYTE8/10 = LOW) into the
Serial Shifter Register at this time slot. This also occurs if the
Encoder is bypassed, the Transmit FIFO is enabled, and the
Transmit FIFO is empty.
External Control of Data Flow
The Transmit Control State Machine supports halting of data
transmission by the TXHALT input. This control signal input is
only interpreted when the Transmit FIFO is enabled. TXHALT is
brought directly to the state machine without going through the
Transmit FIFO.
The assertion of TXHALT causes character processing to stop
at the next FIFO character location. No additional data is read
from the Transmit FIFO until TXHALT is deasserted.
TXHALT may be used to prevent a remote FIFO overflow, which
would result in lost data. This back-pressure mechanism can
significantly improve data integrity in systems that cannot
guarantee the full bandwidth of the host system at all times.
Serial Line Receivers
Two differential line receivers, INA± and INB±, are available for
accepting serial data streams, with the active input selected
using the A/B input. The DLB input allow the transmit Serializer output
to be selected as a third input serial stream, but this path is generally
used only for local diagnostic loopback purposes. The serial line
receiver inputs are all differential, and will accommodate wire inter-
connect with filtering losses or transmission line attenuation greater
than 9 dB (V_DIF > 200 mV, or 400 mV peak-to-peak differential) or can
be directly connected to +5 v fiber-optic interface modules (any ECL
logic family, not limited to ECL 100K). The common-mode tolerance
of these line receivers accommodates a wide range of signal termi-
nation voltages.
As can be seen in Table 2, these inputs are configured to allow
single-pin control for most applications. For those systems
requiring selection of only INA± or INB±, the DLB signals can be tied
LOW, and the A/B selection can be performed using only A/B. For
those systems requiring only a single input and a local loopback,
the A/B can be tied HIGH or LOW, and DLB can be used for
loopback control.
Signal Detect
The selected Line Receiver (that routed to the clock and data
recovery PLL) is simultaneously monitored for:
■analog amplitude (> 400 mV pk-pk)
■transition density
■received data stream outside normal frequency range
(±400 ppm)
■carrier detected.
Notes
6. When SPDSEL is LOW and the FIFOs are bypassed (FIFOBYP is LOW), the RANGESEL input is ignored and is internally mapped to the LOW setting.
7. When configured for 12-bit preencoded data (BYTE8/10 and ENCBYP are both LOW) the allowable REFCLK ranges are 8.33 to 16.67 MHz and 16.67 to
33.33 MHz.
Document #: 38-02020 Rev. *F
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