CY7C14101KV18 Datasheet, PDF (18/31 Pages) Cypress Semiconductor – 36-Mbit QDR® II SRAM 2-Word Burst Architecture

CY7C14101KV18, CY7C14251KV18
CY7C14121KV18, CY7C14141KV18
Identification Register Definitions
Instruction Field
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
ID Register
Presence (0)
CY7C14101KV18
000
11010011010000100
00000110100
1
Value
CY7C14251KV18 CY7C14121KV18
000
000
11010011010001100 11010011010010100
00000110100
00000110100
1
1
CY7C14141KV18
Description
000
Version number.
11010011010100100 Defines the type of
SRAM.
00000110100
Allows unique
identification of
SRAM vendor.
1
Indicates the
presence of an ID
register.
Scan Register Sizes
Instruction
Bypass
ID
Boundary Scan
Register Name
Bit Size
3
1
32
109
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
SAMPLE Z
010
RESERVED
011
SAMPLE/PRELOAD
100
RESERVED
101
RESERVED
110
BYPASS
111
Description
Captures the input and output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-56733 Rev. *E
Page 18 of 31
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