CY28404 Datasheet, PDF (18/20 Pages) Cypress Semiconductor – CK409-COMPLIANT CLOCK SYNTHESIZER

Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
CPUT
33Ω
T_PCB
49.9Ω
33Ω
CPUC
IR E F
475Ω
T_PCB
49.9Ω
M easurem ent
P oint
2pF
M easurem ent
P oint
2pF
CY28404
Figure 8. 0.7V Load Configuration
3.3V sig n als
tD C
-
3 .3 V
O utput under T est
P ro b e
Load Cap
-
2 .4 V
1 .5 V
0 .4 V
0V
Tr
Tf
Figure 9. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement)
Table 11.CPU Clock Current Select Function
Board Target Trace/Term Z
50 Ohms
Reference R, I_REF – V_DD (3*R_REF)
R_REF = 475 1%, I_REF = 2.32mA
Output Current
I_OH = 6*I_REF
V_OH @ Z
0.7V @ 50
Ordering Information
Part Number
CY28404OC
CY28404OCT
Lead Free
CY28404OXC
CY28404OXCT
Package Type
48-pin Shrunk Small Outline package (SSOP)
48-pin Shrunk Small Outline package (SSOP) – Tape and Reel
48-pin Shrunk Small Outline package (SSOP)
48-pin Shrunk Small Outline package (SSOP) – Tape and Reel
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Document #: 38-07510 Rev. *B
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