S6E2C3 Datasheet, PDF (177/198 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C3 Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Parameter
Resolution
Integral nonlinearity
Differential nonlinearity
Zero transition voltage
Full-scale transition
voltage
Conversion time
Symbol
-
-
-
V_ZT
V_FST
-
Sampling time *2
Ts
Pin
Name
-
-
-
ANxx
ANxx
-
-
Compare clock cycle^*3
Tcck
-
Min
-
- 4.5
- 2.5
- 15
AVRH – 15
AV_CC - 15
0.5^*1
0.15
0.3
25
50
Value
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
12
+ 4.5
+ 2.5
+ 15
AVRH + 15
AV_CC + 15
-
10
1000
1000
Unit
bit
LSB
LSB
mV
mV
mV
μs
μs
ns
Remarks
AVRH = 2.7 V to
5.5 V
AV_CC ≥ 4.5 V
AV_CC ≥ 4.5 V
AV_CC < 4.5 V
AV_CC ≥ 4.5 V
AV_CC < 4.5 V
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Power supply current
(analog + digital)
-
AVCC
-
-
Reference power
supply current (AVRH)
-
AVRH
-
-
0.69
0.92
mA
A/D 1 unit
operation
1.3
22
μA
When A/D stop
A/D 1 unit
1.1
1.97
mA
operation
AVRH = 5.5 V
0.3
6.3
μA
When A/D stop
Analog input capacity
C_AIN
Analog input resistance R_AIN
Interchannel disparity
-
Analog port input leak
current
-
Analog input voltage
-
Reference voltage
-
-
-
-
-
ANxx
ANxx
AVRH
AVRL
-
-
-
-
AV_SS
AV_SS
4.5
2.7
AV_SS
-
12.05
pF
-
1.2
kΩ
AV_CC ≥ 4.5 V
1.8
AV_CC < 4.5 V
-
4
LSB
-
5
μA
-
AVRH
V
-
AV_CC
V
-
AVCC
Tcck ＜ 50 ns
V
-
AV_CC
Tcck ≥ 50 ns
-
AV_SS
V
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of Ts = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure
that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting of sampling time and compare
clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part (002-04860). The
register setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus
number to which the A/D converter is connected, see 8. Block Diagram in this data sheet.
The sampling and compare clock are set at base clock (HCLK).
*2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
Document Number: 002-04988 Rev.*A
Page 177 of 198