CY7C2268KV18_12 Datasheet, PDF (17/29 Pages) Cypress Semiconductor – 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2268KV18, CY7C2270KV18
Identification Register Definitions
Instruction Field
Revision number (31:29)
Cypress device ID (28:12)
Cypress JEDEC ID (11:1)
ID register presence (0)
Value
CY7C2268KV18
CY7C2270KV18
000
000
11010111000010111 11010111000100111
00000110100
00000110100
1
1
Description
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Instruction
Bypass
ID
Boundary scan
Register Name
Bit Size
3
1
32
109
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
SAMPLE Z
010
RESERVED
011
SAMPLE/PRELOAD
100
RESERVED
101
RESERVED
110
BYPASS
111
Description
Captures the input and output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-57845 Rev. *E
Page 17 of 29