CY7C1513KV18 Datasheet, PDF (17/31 Pages) Cypress Semiconductor – 72-Mbit QDR-II SRAM 4-Word Burst Architecture

CY7C1511KV18, CY7C1526KV18
CY7C1513KV18, CY7C1515KV18
TAP AC Switching Characteristics
Over the Operating Range ^{[15, 16]}
Parameter
Description
Min
t_TCYC
TCK Clock Cycle Time
50
t_TF
TCK Clock Frequency
t_TH
TCK Clock HIGH
20
t_TL
TCK Clock LOW
20
Setup Times
t_TMSS
TMS Setup to TCK Clock Rise
5
t_TDIS
TDI Setup to TCK Clock Rise
5
t_CS
Capture Setup to TCK Rise
5
Hold Times
t_TMSH
TMS Hold after TCK Clock Rise
5
t_TDIH
TDI Hold after Clock Rise
5
t_CH
Capture Hold after Clock Rise
5
Output Times
t_TDOV
TCK Clock LOW to TDO Valid
t_TDOX
TCK Clock LOW to TDO Invalid
0
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. ^[16]
Figure 2. TAP Timing and Test Conditions
TDO
0.9V
50Ω
Z₀ = 50Ω
C_L = 20 pF
ALL INPUT PULSES
1.8V
0.9V
0V
(a) GND
Test Clock
TCK
Test Mode Select
TMS
Test Data In
TDI
t_TH
t_TL
t_TMSS
t_TMSH
t_TCYC
t_TDIS
t_TDIH
Max
20
10
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Data Out
TDO
t_TDOV
t_TDOX
Notes
15. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. t_R/t_F = 1 ns.
Document Number: 001-00435 Rev. *E
Page 17 of 31
[+] Feedback