CY7C1370DV25 Datasheet, PDF (17/30 Pages) Cypress Semiconductor – 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture

PRELIMINARY
119-ball BGA Boundary Scan Order^{[12, 13]}
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CY7C1372DV25 (2M x 18)
Ball ID
Bit #
H4
37
T4
38
T5
39
T6
40
R5
41
L5
42
R6
43
U6
44
R7
45
T7
46
P6
47
N7
48
M6
49
L7
50
K6
51
P7
52
N6
53
L6
54
K7
55
J5
56
H6
57
G7
58
F6
59
E7
60
D7
61
H7
62
G6
63
E6
64
D6
65
C7
66
B7
67
C6
68
A6
69
C5
70
B5
71
G5
72
Ball ID
B6
D4
B4
F4
M4
A5
K4
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
G1
H2
D1
E2
G2
H1
J3
2K
L1
M2
N1
P1
K1
L2
CY7C1372DV25 (2M x 18)
Bit #
Ball ID
73
N2
74
P2
75
R3
76
T1
77
R1
78
T2
79
L3
80
R2
81
T3
82
L4
83
N4
84
P4
85
Internal
CY7C1370DV25
CY7C1372DV25
Document #: 38-05558 Rev. *A
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