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| CY7C0837V Datasheet, PDF (17/28 Pages) Cypress Semiconductor – FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM | |||
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PRELIMINARY
CY7C0837V
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
Switching Waveforms (continued)
Bank Select Read[33, 34]
CLK
tSA
ADDRESS(B1)
tSC
CE(B1)
tCYC2
tCH2
tCL2
tHA
A0
A1
tHC
tCD2
A2
tSC tHC tCD2
DATAOUT(B1)
tSA
tHA
ADDRESS(B2)
A0
A1
CE(B2)
tSC
tHC
DATAOUT(B2)
Q0
tDC
A2
tSC
tHC
Read-to-Write-to-Read (OE = LOW)[32, 35, 36, 37, 38]
tCYC2
tCH2
tCL2
CLK
A3
tCKHZ
Q1
tDC
A3
tCD2
tCKLZ
A4
A5
tCD2
tCKLZ
A4
tCKHZ
Q3
A5
tCKHZ
Q2
tCD2
Q4
tCKLZ
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
tHA
DATAIN
An+1
tCD2
An+2
tCKHZ
An+2
tSD tHD
Dn+2
An+3
An+4
tCD2
DATAOUT
READ
Qn
NO OPERATION
WRITE
tCKLZ
READ
Qn+3
Notes:
33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
34. ADS = CNTEN= BE0 â BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
36. During âNo Operation,â data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
37. CE0 = OE = BE0 â BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
38. CE0 = BE0 â BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06059 Rev. *K
Page 17 of 28
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