CYV15G0203TB_07 Datasheet, PDF (16/20 Pages) Cypress Semiconductor – Independent Clock Dual HOTLink II™ Serializer

CYV15G0203TB
CYV15G0203TB HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface
TXCLKOx Timing
TXRATEx = 1
REFCLKx
Note 22
t_REFH
t_TXCLKO
t_REFCLK
Note 21
t_REFL
TXCLKOx
(internal)
Transmit Interface
TXCLKOx Timing
TXRATEx = 0
REFCLKx
TXCLKOx
Note 22
t_REFCLK
t_REFH
Note 21
t_{tTTXXCCLLKKOO}
t_REFL
CYV15G0203TB HOTLink II Bus Configuration Switching Waveforms
Bus Configuration
Write Timing
ADDR[2:0]
DATA[3:0]
WREN
t_DATAS
t_WRENP
t_DATAH
Notes
21. The TXCLKOx output remains at the character rate regardless of the state of TXRATEx and does not follow the duty cycle of REFCLKx±.
22. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input.
Document #: 38-02105 Rev. *C
Page 16 of 20
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