CY7C161KV18 Datasheet, PDF (16/32 Pages) Cypress Semiconductor – 144-Mbit DDR II SRAM Two-Word Burst Architecture

CY7C1618KV18, CY7C1620KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter ^{[16, 17]}
t_TCYC
t_TF
t_TH
t_TL
Setup Times
TCK clock cycle time
TCK clock frequency
TCK clock high
TCK clock low
t_TMSS
t_TDIS
t_CS
Hold Times
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
t_TMSH
t_TDIH
t_CH
Output Times
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
t_TDOV
t_TDOX
TCK clock low to TDO valid
TCK clock low to TDO invalid
Description
Min
Max Unit
50
–
ns
–
20
MHz
20
–
ns
20
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
–
10
ns
0
–
ns
Notes
16. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions. t_R/t_F = 1 ns.
Document Number: 001-44274 Rev. *H
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