CY7C1484BV33 Datasheet, PDF (16/30 Pages) Cypress Semiconductor – 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

CY7C1484BV33
Identification Register Definitions
Bit# 24 is “1” in the ID Register definitions for both 2.5 V and 3.3 V versions of the device.
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
Architecture/Memory Type(23:18)
Bus Width/Density (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
CY7C1484BV33
(2 M × 36)
000
01011
000110
100100
00000110100
1
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
Enables unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan Order – 165-ball FBGA
Bit Size (× 36)
3
1
32
73
Identification Codes
Instruction
EXTEST
IDCODE
Code
000
001
SAMPLE Z
010
RESERVED
011
SAMPLE/PRELOAD
100
RESERVED
101
RESERVED
110
BYPASS
111
Description
Captures I/O ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-75351 Rev. *B
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