CY7C1460AV33_06 Datasheet, PDF (16/27 Pages) Cypress Semiconductor – 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

209-ball BGA Boundary Scan Order ^{[13, 14]}
CY7C14604V33 (512K x 72)
Bit#
Ball ID
Bit#
1
W6
36
2
V6
37
3
U6
38
4
W7
39
5
V7
40
6
U7
41
7
T7
42
8
V8
43
9
U8
44
10
T8
45
11
V9
46
12
U9
47
13
P6
48
14
W11
49
15
W10
50
16
V11
51
17
V10
52
18
U11
53
19
U10
54
20
T11
55
21
T10
56
22
R11
57
23
R10
58
24
P11
59
25
P10
60
26
N11
61
27
N10
62
28
M11
63
29
M10
64
30
L11
65
31
L10
66
32
K11
67
33
M6
68
34
L6
69
35
J6
70
ball ID
6F
8K
9K
10K
11J
10J
11H
10H
11G
10G
11F
10F
10E
11E
11D
10D
11C
10C
11B
10B
11A
10A
9C
9B
9A
8D
8C
8B
8A
7D
7C
7B
7A
6D
6G
Note:
14. Bit# 138 is preset HIGH.
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Bit#
ball ID
71
6H
72
6C
73
6B
74
6A
75
5A
76
5B
77
5C
78
5D
79
4D
80
4C
81
4A
82
4B
83
3C
84
3B
85
3A
86
2A
87
1A
88
2B
89
1B
90
2C
91
1C
92
2D
93
1D
94
1E
95
2E
96
2F
97
1F
98
1G
99
2G
100
2H
101
1H
102
2J
103
1J
104
1K
105
6N
Bit#
ball ID
106
3K
107
4K
108
6K
109
2K
110
2L
111
1L
112
2 Mbit
113
1 Mbit
114
2N
115
1N
116
2P
117
1P
118
2R
119
1R
120
2T
121
1T
122
2U
123
1U
124
2V
125
1V
126
2W
127
1W
128
6T
129
3U
130
3V
131
4T
132
5T
133
4U
134
4V
135
5W
136
5V
137
5U
138
Internal
Document #: 38-05353 Rev. *D
Page 16 of 27
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