CY7C1411BV18 Datasheet, PDF (16/28 Pages) Cypress Semiconductor – 36-Mbit QDR™-II SRAM 4-Word Burst Architecture

PRELIMINARY
CY7C1411BV18
CY7C1426BV18
CY7C1413BV18
CY7C1415BV18
TAP AC Switching Characteristics Over the Operating Range ^{[13, 14]} (continued)
Parameter
Description
Output Times
t_TDOV
t_TDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Min.
Max.
Unit
10
ns
0
ns
TAP Timing and Test Conditions^[14]
TDO
0.9V
50Ω
Z₀ = 50Ω
C_L = 20 pF
ALL INPUT PULSES
1.8V
0.9V
0V
GND
(a)
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
t_TH
t_TL
t_TMSS
t_TCYC
t_TMSH
t_TDIS
t_TDIH
Test Data-Out
TDO
t_TDOV
t_TDOX
Identification Register Definitions
Instruction Field
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC
ID (11:1)
ID Register
Presence (0)
CY7C1411BV18
001
11010011011000111
00000110100
1
Value
CY7C1426BV18
CY7C1413BV18
001
001
11010011011001111 11010011011010111
00000110100
00000110100
1
1
CY7C1415BV18 Description
001
Version
number.
11010011011100111 Defines the
type of SRAM.
00000110100
Allows unique
identification of
SRAM vendor.
1
Indicates the
presence of an
ID register.
Document Number: 001-07037 Rev. *B
Page 16 of 28