CY7C1312CV18_11 Datasheet, PDF (16/26 Pages) Cypress Semiconductor – 18-Mbit QDR® II SRAM 2-Word Burst Architecture

CY7C1312CV18
CY7C1314CV18
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
CY7C1312CV18
000
11010011010010101
00000110100
Value
CY7C1314CV18
000
11010011010100101
00000110100
ID Register Presence (0)
1
1
Description
Version number.
Defines the type of SRAM.
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Scan Register Sizes
Instruction
Bypass
ID
Boundary Scan
Register Name
Bit Size
3
1
32
107
Instruction Codes
Instruction
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Code
000
001
010
011
100
101
110
111
Description
Captures the input and output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
Captures the input and output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input and output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document #: 001-07164 Rev. *H
Page 16 of 26
[+] Feedback