CY28341-2 Datasheet, PDF (16/19 Pages) Cypress Semiconductor – Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems

CY28341-2
AC Parameters (continued)
100 MHz
133 MHz
200 MHz
Parameter
Description
Min. Max. Min. Max Min. Max. Unit Notes
T_R/T_F
CPUT/C Rise and Fall Times
Rise/Fall Matching
175 700 175 700 175 700 ps 24
20%
20%
20%
24,26
∆ T_R/T_F
Rise/Fall Time Variation
T_SKEW
CPUCS_T/C to CPUT/C Clock Skew
T_CCJ
CPUT/C Cycle to Cycle Jitter
V_CROSS
Crossing Point Voltage at 0.7V Swing
P4 Mode CPU at 1.0V
0
–150
280
125
200
+150
430
0
–150
280
125
150
+150
430
0
–200
280
125
200
+200
430
ps 8,24,16
ps 8,18,15,16
ps 8,18,15,16
mV 16
T_DC
CPUT/C Duty Cycle
T_PERIOD
CPUT/C Period
Differential CPUT/C Rise and Fall times
T_R/T_F
T_SKEW
CPUCS_T/C to CPUT/C Clock Skew
T_CCJ
CPUT/C Cycle to Cycle Jitter
V_CROSS
Crossing Point Voltage at 1V Swing
SE-DeltaSlew Absolute Single-ended Rise/Fall
Waveform Symmetry
45
9.85
175
0
–150
510
55
10.2
467
200
+150
760
325
45
55
45
55 % 8,9,15
7.35 7.65 4.85 5.1 nS 8,9,15
175 467 175 467 ps 7,14,27
0
–150
510
150
+150
760
325
0
–200
510
200
+200
760
325
0 8,14,11
ps 8,14,11
mV 27
ps 26
K7 Mode
T_DC
CPUOD_T/C Duty Cycle
T_PERIOD
CPUOD_T/C Period
T_LOW
CPUOD_T/C Low Time
T_F
CPUOD_T/C Fall Time
T_SKEW
CPUCS_T/C to CPUT/C Clock Skew
T_CCJ
CPUOD_T/C Cycle-to-Cycle Jitter
V_D
Differential Voltage AC
V_X
Differential Crossover Voltage
CHIPSET CLOCK
45
9.98
2.8
0.4
0
–150
.4
500
55
10.5
1.6
200
+150
Vp+.6V
1100
45
7.5
1.67
0.4
0
–150
.4
500
55
8.0
1.6
150
+150
Vp+.6V
1100
45
5
2.8
0.4
0
–200
.4
500
55 % 8,9
5.5 ns 8,9
ns 8,9
1.6 ns 8,13
200 0 8,14,11
+200 ps 8,9
Vp+.6V V 23
1100 mV 23
T_DC
T_PERIOD
T_R / T_F
V_D
V_X
AGP
CPUCS_T/C Duty Cycle
CPUCS_T/C Period
CPUCS_T/C Rise and Fall Times
Differential Voltage AC
Differential Crossover Voltage
45
55
45
55
45
55 % 7,8,9
10.0 10.5
15 15.5 10.0 10.5 ns 7,8,9
0.4
1.6
0.4 1.6 0.4 1.6 ns 7,8,13
.4 Vp+.6V .4 Vp+.6V .4 Vp+.6V V 24
0.5*V_D 0.5*V_DDI 0.5*V_D 0.5*V_D 0.5*V_D 0.5*V_D V 11
D^{I–0.2 +0.2} D^I–0.2 D^I+0.2 D^I–0.2 D^I+0.2
T_DC
AGP(0:2) Duty Cycle
45
55
45
55
45
55 % 7,8,9
T_PERIOD
AGP(0:2) Period
15
16
15
16
15
16 ns 7,8,9
T_HIGH
AGP(0:2) High Time
5.25
5.25
5.25
ns 8,21
T_LOW
AGP(0:2) Low Time
5.05
5.05
5.05
ns 8,10
T_R / T_F
AGP(0:2) Rise and Fall Times
0.4
1.6
0.4 1.6 0.4 1.6 ns 8,13
Notes:
17. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
between 20% and 80% for differential signals.
18. This measurement is applicable with Spread ON or spread OFF.
19. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals).
20. Time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till frequency output is stable and operating within specs.
21. The typical value of VX is expected to be 0.5*V_DDD (or 0.5*V_DDC for CPUCS signals) and will track the variations in the DC level of the same.
22. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its comple-
mentary DDRC (and CPUCS_C) one.
23. Measured at VX between the rising edge and the following falling edge of the signal.
24. Measured from V_OL = 0.175V to V_OH = 0.525V.
25. Measurement taken from differential waveform, from –0.35V to +0.35V.
26. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as “the instantaneous
difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is
designed for waveform symmetry.
27. Measured in absolute voltage, i.e., single-ended measurement.
Document #: 38-07471 Rev. *B
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