CY7C43643 Datasheet, PDF (15/29 Pages) Cypress Semiconductor – 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

CY7C43643
CY7C43663
CY7C43683
Switching Characteristics Over the Operating Range (continued)
CY7C43643/
63/83
–7
CY7C43643/
63/83
–10
CY7C43643/
63/83
–15
Parameter
Description
t_SKEW1[18] Skew Time between CLKA↑ and CLKB↑ for EF/OR
and FF/IR
t_SKEW2[18] Skew Time between CLKA↑ and CLKB↑ for AE
and AF
Min.
5
7
Max.
Min.
5
8
Max.
Min.
7.5
12
Max. Unit
ns
ns
t_A
t_WFF
t_REF
t_PAE
t_PAF
t_PMF
t_PMR
t_MDV
t_RSF
Access Time, CLKA↑ to A_0–35 and CLKB↑ to B_0–35 1
6
1
8
3
10
ns
Propagation Delay Time, CLKA↑ to FF/IR
1
6
1
8
2
8
ns
Propagation Delay Time, CLKB↑ to EF/OR
1
6
1
8
1
8
ns
Propagation Delay Time, CLKB↑ to AE
1
6
1
8
1
8
ns
Propagation Delay Time, CLKA↑ to AF
1
6
1
8
1
8
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or 0
6
0
8
0
12
ns
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
Propagation Delay Time,
CLKB↑ to A_{0–35[20]}
CLKA↑
to
B_{0–35[19]}
and
1
7
2
11
3
12
ns
Propagation Delay Time, MBA to A_0–35 Valid and
1
6
2
9
3
11
ns
MBB to B_0–35 Valid
Propagation Delay Time, MRS1/MRS2 or PRS
1
6
1
10
1
15
ns
LOW to AE LOW, AF HIGH, FF/IR LOW, EF/OR
LOW and MBF1/MBF2 HIGH
t_EN
Enable Time, CSA or W/RA LOW to A_0–35 Active
1
6
2
8
2
10
ns
and CSB LOW and W/RB HIGH to B_0–35 Active
t_DIS
Disable Time, CSA or W/RA HIGH to A_0–35 at High 1
5
1
6
1
8
ns
Impedance and CSB HIGH or W/RB LOW to B_0–35
at High Impedance
t_RTR
Retransmit Recovery Time
90
90
90
ns
Notes:
18. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
19. Writing data to the Mail1 register when the B_0–35 outputs are active and MBB is HIGH.
20. Writing data to the Mail2 register when the A_0–35 outputs are active and MBA is HIGH.
Document #: 38-06021 Rev. *B
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