CY7C1562XV18 Datasheet, PDF (15/29 Pages) Cypress Semiconductor – 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1562XV18, CY7C1564XV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter ^{[15, 16]}
Description
t_TCYC
t_TF
t_TH
t_TL
Setup Times
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
t_TMSS
t_TDIS
t_CS
Hold Times
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
t_TMSH
t_TDIH
t_CH
Output Times
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
t_TDOV
t_TDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Min
Max Unit
50
–
ns
–
20
MHz
20
–
ns
20
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
–
10
ns
0
–
ns
Notes
15. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. t_R/t_F = 1 ns.
Document Number: 001-68998 Rev. *B
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