CY7C1516JV18 Datasheet, PDF (15/26 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 2-Word Burst Architecture

TAP Controller Block Diagram
CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
TDI
Selection
Circuitry
TCK
TMS
0
Bypass Register
210
Instruction Register
31 30 29 . . 2 1 0
Identification Register
108 . . . . 2 1 0
Boundary Scan Register
Selection
Circuitry
TAP Controller
TDO
TAP Electrical Characteristics
Over the Operating Range ^{[10, 11, 12]}
Parameter
Description
V_OH1
V_OH2
V_OL1
V_OL2
V_IH
V_IL
I_X
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and Output Load Current
Test Conditions
I_OH = −2.0 mA
I_OH = −100 μA
I_OL = 2.0 mA
I_OL = 100 μA
GND ≤ V_I ≤ V_DD
Min
Max
Unit
1.4
V
1.6
V
0.4
V
0.2
V
0.65V_DD V_DD + 0.3
V
–0.3 0.35V_DD
V
–5
5
μA
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
11. Overshoot: V_IH(AC) < V_DDQ + 0.85V (Pulse width less than t_CYC/2), Undershoot: V_IL(AC) > −1.5V (Pulse width less than t_CYC/2).
12. All Voltage referenced to Ground.
Document Number: 001-12559 Rev. *C
Page 15 of 26
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