CY7C1471V33_13 Datasheet, PDF (15/23 Pages) Cypress Semiconductor – 72-Mbit (2 M x 36) Flow-Through SRAM with NoBL™ Architecture

CY7C1471V33
Switching Waveforms (continued)
Figure 5. ZZ Mode Timing ^{[28, 29]}
CLK
t _ZZ
ZZ
t _ZZI
t _ZZREC
I _SUPPLY
ALL INPUTS
(except ZZ)
I _DDZZ
t _RZZI
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
28. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device.
29. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05288 Rev. *Q
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