CY7C1470BV33 Datasheet, PDF (15/30 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

TAP AC Switching Characteristics
Over the Operating Range^{[9, 10]}
Parameter
Description
Clock
t_TCYC
TCK Clock Cycle Time
t_TF
TCK Clock Frequency
t_TH
TCK Clock HIGH time
t_TL
TCK Clock LOW time
Output Times
t_TDOV
TCK Clock LOW to TDO Valid
t_TDOX
TCK Clock LOW to TDO Invalid
Setup Times
t_TMSS
TMS Setup to TCK Clock Rise
t_TDIS
TDI Setup to TCK Clock Rise
t_CS
Capture Setup to TCK Rise
Hold Times
t_TMSH
t_TDIH
t_CH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Min
Max
Unit
50
ns
20
MHz
20
ns
20
ns
10
ns
0
ns
5
ns
5
ns
5
ns
5
ns
5
ns
5
ns
Notes
9. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. t_R/t_F = 1 ns.
Document #: 001-15031 Rev. *C
Page 15 of 30
[+] Feedback