CY7C1392BV18 Datasheet, PDF (15/27 Pages) Cypress Semiconductor – 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
TAP AC Switching Characteristics Over the Operating Range (continued)^{[11, 12]}
Parameter
Description
t_CS
Capture Set-up to TCK Rise
Hold Times
t_TMSH
TMS Hold after TCK Clock Rise
t_TDIH
TDI Hold after Clock Rise
t_CH
Capture Hold after Clock Rise
Output Times
t_TDOV
t_TDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TAP Timing and Test Conditions^[12]
Min.
Max.
Unit
5
ns
5
ns
5
ns
5
ns
10
ns
0
ns
0.9V
TDO
50Ω
Z₀ = 50Ω
C_L = 20 pF
(a)
GND
ALL INPUT PULSES
1.8V
0.9V
0V
t_TH
t_TL
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
t_TMSS
t_TDIS
t_TCYC
t_TMSH
t_TDIH
Test Data-Out
TDO
t_TDOV
t_TDOX
Document Number: 38-05623 Rev. *C
Page 15 of 27
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