CY7C1371S Datasheet, PDF (15/29 Pages) Cypress Semiconductor – 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture

CY7C1371S
3.3 V TAP AC Test Conditions
Input pulse levels ...............................................V_SS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
3.3 V TAP AC Output Load Equivalent
1.5V
TDO
Z_O= 50Ω
50Ω
20pF
2.5 V TAP AC Test Conditions
Input pulse level ................................................. V_SS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ...................................... .1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
2.5 V TAP AC Output Load Equivalent
1.25V
TDO
Z_O= 50Ω
50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < T_A < +70 °C; V_DD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter ^[11]
Description
Conditions
V_OH1
V_OH2
V_OL1
V_OL2
V_IH
V_IL
I_X
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
I_OH = –4.0 mA
I_OH = –1.0 mA
I_OH = –100 µA
I_OL = 8.0 mA
I_OL = 1.0 mA
I_OL = 100 µA
GND < V_IN < V_DDQ
V_DDQ = 3.3 V
V_DDQ = 2.5 V
V_DDQ = 3.3 V
V_DDQ = 2.5 V
V_DDQ = 3.3 V
V_DDQ = 2.5 V
V_DDQ = 3.3 V
V_DDQ = 2.5 V
V_DDQ = 3.3 V
V_DDQ = 2.5 V
V_DDQ = 3.3 V
V_DDQ = 2.5 V
Min
Max Unit
2.4
–
V
2.0
–
V
2.9
–
V
2.1
–
V
–
0.4
V
–
0.4
V
–
0.2
V
–
0.2
V
2.0
1.7
–0.5
V_DD + 0.3 V
V_DD + 0.3 V
0.7
V
–0.3
0.7
V
–5
5
µA
Note
11. All voltages referenced to V_SS (GND).
Document Number: 001-43826 Rev. *F
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