CY7C1364C Datasheet, PDF (15/18 Pages) Cypress Semiconductor – 9-Mbit (256K x 32) Pipelined Sync SRAM

Switching Waveforms (continued)
ZZ Mode Timing^{[22, 23]}
CLK
t _ZZ
ZZ
t _ZZI
I _SUPPLY
ALL INPUTS
(except ZZ)
I _DDZZ
Outputs (Q)
CY7C1364C
t _ZZREC
High-Z
DON’T CARE
t _RZZI
DESELECT or READ Only
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05689 Rev. *E
Page 15 of 18
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