CY7B993V_05 Datasheet, PDF (15/15 Pages) Cypress Semiconductor – High-speed Multi-phase PLL Clock Buffer

RoboClock^
CY7B993V
CY7B994V
Document History Page
Document Title: RoboClock^ CY7B994V/CY7B993V High-speed Multi-phase PLL Clock Buffer
Document Number: 38-07127
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
**
109957 12/16/01
SZV Changed from Spec number: 38-00747 to 38-07127
*A
114376 05/06/02
CTK Added three industrial packages
*B
116570 09/04/02 HWT Added TTB Features
*C
122794 12/14/02
RBI Power-up requirements to operating conditions information
*D
123694 03/04/03
RGL Added min. F_out value of 12 MHz for CY7B993V and 24 MHz for CY7B994V
to switching characteristics table
Corrected prop delay limit parameter from (t_PDSL,M,H) to t_PD in the Lock Detect
Output Description paragraph
*E
128462 07/29/03
RGL Added clock input frequency (f_in) specifications in the switching characteristics
table
*F
391560 See ECN RGL Added Lead-free devices
Added typical values for jitter
Document #: 38-07127 Rev. *F
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