CY14C512I_13 Datasheet, PDF (15/41 Pages) Cypress Semiconductor – 512-Kbit (64 K x 8) Serial (I2C) nvSRAM with Real Time Clock

CY14C512I
CY14B512I
CY14E512I
Current Address RTC Registers Read
A current read of RTC registers starts with the master sending
the RTC Registers Slave address after the START condition. All
read operations begin from the current address (the address
next to previously accessed address location). After the last
address is read sequentially, the address latch loops back to the
first location (0x00) and read operation continues. The master
may terminate a read operation after reading one byte or
continue reading addresses sequentially till the last address in
the memory after which the address counter rolls back to the
address 0x00. A read operation may be terminated by the master
by generating a STOP condition or a Repeated START operation
or a NACK.
Figure 25. Current Address RTC Registers Single-Byte Read
By Master
S
T
A
R ^{RTC Registers Slave Address}
T
S
T
A0
P
SDA Line
S 1 1 0 1 A2 A1 A0 1
P
By nvSRAM
Data Byte
A
By Master
SDA Line
By nvSRAM
Figure 26. Current Address RTC Registers Multi-Byte Read
S
T
A
A
R RTC Registers Slave Address
T
S 1 1 0 1 A2 A1 A0 1
A
Data Byte 1
Data Byte N
S
AT
0
P
P
Random Address RTC Registers Read
A random address read is performed by first initiating a write
operation and generating a Repeated START immediately after
the last address byte is acknowledged. The address counter is
set to this address and the next read access to this slave initiates
the read operation from here. The master may terminate a read
operation after reading one byte or continue reading addresses
sequentially till the last address in the memory after which the
address counter rolls back to the start address location of RTC
(0x00).
A random address read attempt on an out of bound memory
address on the RTC Registers Slave is responded back with a
NACK from the nvSRAM after the address byte is transmitted.
The address counter remains unaffected and the following
current read operation starts from the address value held in the
address counter.
By Master
SDA Line
Figure 27. Random Address RTC Registers Single-Byte Read
S
T
A
R
T
RTC Registers Slave Address
RTC Register Address
RTC Registers Slave Address
S 1 1 0 1 A2 A1 A0 0
Sr 1 1 0 1 A2 A1 A0 1
S
T
A0
P
P
By nvSRAM
A
A
Data Byte
A
Figure 28. Random Address RTC Registers Multi-Byte Read
S
T
A
R
A
By Master
T ^{RTC Registers Slave Address}
RTC Register Address
RTC Registers Slave Address
SDA Line
BynvSRAM
S 1 1 0 1 A2 A1 A0 0
A
Sr 1 1 0 1 A2 A1 A0 1
A
A
Data Byte 1
Data Byte N
S
T
A0
P
P
Document Number: 001-64879 Rev. *G
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