CYU01M16ZCC Datasheet, PDF (14/14 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Pseudo Static RAM

PRELIMINARY
CYU01M16ZCC
MoBL3™
Document History Page
Document Title: CYU01M16ZCC MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM
Document Number: 38-05602
REV.
ECN NO.
Issue
Date
Orig. of
Change Description of Change
**
278869 See ECN SYT New Data Sheet
*A
280850 See ECN REF Updated the Ordering information to show lead-free offering.
*B
314034 See ECN
PCI Corrected Part Number
Added Operating Range in Features Section
Moved address lines A8 - A10 from Column decoder to Row decoder in the
Logic Block Diagram
Changed Pin Configuration Diagram Name from FBGA to VFBGA
Modified description on Deep Sleep Mode
Changed t_ZZWE description
Changed Θ_JA and Θ_JC from 55 and 17 °C/W to 56 and 11°C/W respectively
Changed R1, R2 and RTH from 22000, 22000 and 11000 Ω to 26000, 26000
and 13000 Ω respectively
Modified Test Condition for I_IX and I_OZ
Removed note # 18 from *A rev
Changed V_CC(typ) to V_CC in note # 12
Changed V_OL Max., to 0.2 from 0.2 * V_CC
Changed t_OHA from 10 ns to 5 ns
Changed t_SCE, t_AW and t_BW from 45 to 50 ns
Changed t_RC and t_WC from 6000 ns to 40000 ns
Changed t_PC and t_PA from 15 ns to 20 ns
Added Parameter t_CD in AC Table and its corresponding footnote in Notes
Section
Parameter t_CD added in Read Cycle 2 and Write Cycle 1 Timing Diagrams
Changed from Advance Information to Preliminary
*C
351766 See ECN
PCI Modified Logic Block Diagram
Modified description on Deep Sleep Mode
Deleted Page Write in the Page Mode Feature Table
Added CE, BHE and BLE in test conditions for I_ZZ in DC Table
Modified condition in the third row of the Truth Table for ZZ Pin from X to H
*D
386551 See ECN
PCI
Changed t_PC and t_PA from 20 to 25 ns
Replaced TBDs with appropriate values
*E
406266 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”.
Removed 55 ns Speed Bin.
Removed BHE, BLE in the DPD entry waveform on page #3.
Included ZZ in power-up characteristics on page #5.
Added I_SB1 specification in the DC characteristics table on page #6.
Added test condition ZZ>= V_CC-0.2V for ISB₂
Updated the Truth Table for DPD / PAR and Write (Variable Address Mode
Register) Modes.
*F
420604 See ECN HRT Changed T_CD value to 15 ns from 5 ns on Read and Write Cycles
Changed T_PC and T_PAA values to 35 ns from 25 ns
Included “Chip Enable Access” footnote in AC Parameters
Changed Isb2 value from 60µA to 70µA
Document #: 38-05602 Rev. *F
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