CYII4SC014KAA-GTC_09 Datasheet, PDF (14/27 Pages) Cypress Semiconductor – Megapixel CMOS Image Sensor

CYII4SC014KAA-GTC
CYII4SM014KAA-GEC
Pin Configuration
Table 8 lists the pin configuration of the IBIS4-14000. Figure 16 on page 21 shows the assignment of pin numbers on the package.
Table 8. Pinout Configuration
Pin #
Name
1
OBIAS
Function
Bias current output amplifiers.
2
GND
Ground for output 3.
Comment
Connect with 10kΩ to VDD and decouple with 100 nF to
GND.
3
OUT3
4
GND
5
OUT4
6
VDD
7
GND
8
OUT2
9
GND
10
OUT1
11
GND
Output 3.
Ground for output 4.
Output 4.
Power supply.
Ground.
Output 2.
Ground for output 2.
Output 1.
Ground for output 1.
Nominal 3.3V
0V
12
DARKREF Offset level of output signal.
Typ. 2.6V. min. 1.7V max. 3V
13
TEMP1
Temperature sensor.
Any voltage above GND forward biases the diode.
Located near the output amplifiers (pixel Connect to GND if not used.
4536, 0) near the stitch line).
14
PHDIODE Photodiode output.
Reverse biased by any voltage above GND
Yields the equivalent photocurrent of 250 x Connect to GND if not used.
50 pixels. Diode is located right under the
pad.
15
CLK_Y
Y clock for switchboard.
Clocks on rising edge
Connect to CLK_YL (or drive identically)
16
SYNC_Y Y SYNC pulse for switchboard.
Low active: synchronous sync on rising edge of CLK_Y
Connect to SYNC_YL (or drive identically)
17
TEMP2
Temperature sensor.
Located near pixel (24,0).
Any voltage above GND forward biases the diode.
Connect to GND if not used.
18
GNDAB
Anti-blooming reference level (= pin 33). Typ. 0V. Set to 1.5V for improved anti-blooming.
19
GND
Ground.
0V
20
VDD
Power supply.
Nominal 3.3V
21
VDDR
Power supply for reset line drivers
Nominal 4V
Connected on-chip to pin 30
22
CLK_YR Clock of YR shift register.
Shifts on rising edge.
23
SYR
Activate YR shift register for driving of reset High active. Exact pulsing pattern see timing diagram.
and select line of pixel array.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected!
24
SYNC_YR Sets the YR shift register to row 1.
Low active. Synchronous sync on rising edge of CLK_YR
200 ns setup time
25
VDDARRAY Pixel array power supply (= pin 26).
3V
26
VDDARRAY Pixel array power supply (= pin 25).
3V
27
SYNC_YL Sets the YL shift register to row 1.
Low active. Synchronous sync on rising edge of CLK_YL
200 ns setup time.
28
SYL
Activate YL shift register for driving of reset High active. Exact pulsing pattern see timing diagram.
and select line of pixel array.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected.
Document #: 38-05709 Rev. *C
Page 14 of 27
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