CY8C29466_09 Datasheet, PDF (14/46 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

CY8C29466, CY8C29566
CY8C29666, CY8C29866
8.5 100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device.
Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production
Table 8-6. 100-Pin OCD Part Pinout (TQFP)
Pin
No.
Name
Description
Pin
No.
Name
Description
1
NC No internal connection.
2
NC No internal connection.
3 IO I P0[1] Analog column mux input.
4 IO
P2[7]
5 IO
P2[5]
6 IO I P2[3] Direct switched capacitor block input.
7 IO I P2[1] Direct switched capacitor block input.
8 IO
P4[7]
9 IO
P4[5]
10 IO
P4[3]
11 IO
P4[1]
12
OCDE OCD even data IO
13
OCDO OCD odd data output
14 Power SMP Switch Mode Pump (SMP) connection to
required external components.
15 Power Vss Ground connection.
16 IO
P3[7]
17 IO
P3[5]
18 IO
P3[3]
19 IO
P3[1]
20 IO
P5[7]
21 IO
P5[5]
22 IO
P5[3]
23 IO
P5[1]
24 IO
P1[7] I2C Serial Clock (SCL)
25
NC No internal connection.
26
NC No internal connection.
27
NC No internal connection.
28 IO
P1[5] I2C Serial Data (SDA).
29 IO
P1[3] I_FMTEST
51
52 IO
53 IO
54 IO
55 IO
56 IO
57 IO
58 IO
59 IO
60
61
62 Input
63 IO
64 IO
65 Power
66 IO
67 IO
68 IO I
69 IO I
70 IO
71
72 IO
73
74 IO I
75
76
77 IO IO
78
79 IO IO
30 IO
P1[1]* Crystal (XTALin), I2C Serial Clock (SCL), TC 80
SCLK.
31
NC No internal connection.
81 IO I
32 Power Vdd Supply voltage.
82 Power
33
NC No internal connection.
83 Power
34 Power Vss Ground connection.
84 Power
35
NC No internal connection.
85 Power
36 IO
P7[7]
86 IO
37 IO
P7[6]
87 IO
38 IO
P7[5]
88 IO
39 IO
P7[4]
89 IO
40 IO
P7[3]
90 IO
41 IO
P7[2]
91 IO
42 IO
P7[1]
92 IO
43 IO
P7[0]
93 IO
44 IO
P1[0]* Crystal (XTALout), I2C Serial Data (SDA), TC 94
SDATA
45 IO
46 IO
P1[2] V_FMTEST
P1[4] Optional External Clock Input (EXTCLK)
95 IO I
96
47 IO
P1[6]
97 IO IO
48
NC No internal connection.
98
49
NC No internal connection.
99 IO IO
50
NC No internal connection.
100
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test.
* ISSP pin which is not HiZ at POR.
NC
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
HCLK
CCLK
XRES
P4[0]
P4[2]
No internal connection.
OCD high speed clock output
OCD CPU clock output
Active high pin reset with internal pull down.
Vss
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
NC
P2[6]
NC
P0[0]
NC
NC
P0[2]
NC
P0[4]
NC
Ground connection.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
No internal connection.
External Voltage Reference (VREF) input.
No internal connection.
Analog column mux input.
No internal connection.
No internal connection.
Analog column mux input and column output.
No internal connection.
Analog column mux input and column output,
V_REF.
No internal connection.
P0[6]
Vdd
Vdd
Vss
Vss
P6[0]
P6[1]
P6[2]
P6[3]
P6[4]
P6[5]
P6[6]
P6[7]
NC
Analog column mux input.
Supply voltage.
Supply voltage.
Ground connection.
Ground connection.
No internal connection.
P0[7]
NC
P0[5]
NC
P0[3]
NC
Analog column mux input.
No internal connection.
Analog column mux input and column output.
No internal connection.
Analog column mux input and column output.
No internal connection.
Document Number: 38-12013 Rev. *K
Page 14 of 46
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