CY8C24094_09 Datasheet, PDF (14/47 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

CY8C24094, CY8C24794
CY8C24894, CY8C24994
Table 7-6. 100-Ball Part Pinout (VFBGA) (continued)
C8 I/O I,M
C9 I/O M
C10
D1
D2 I/O M
D3 I/O M
D4 I/O M
D5 I/O I/O,
M
D6 I/O I,M
D7 I/O M
D8 I/O M
D9 I/O M
D10
E1
E2
E3 I/O M
E4 I/O I,M
E5 Power
E6 Power
E7 I/O M
E8 I/O M
E9 I/O M
E10
P2[0]
P4[2]
NC
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
CCLK
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
HCLK
Direct switched capacitor block input.
H8 I/O M
H9 I/O M
No connection.
H10 I/O
No connection.
J1 Power
J2 Power
J3 USB
J4 USB
Analog column mux input and column output. J5 Power
Analog column mux input.
External Voltage Reference (VREF) input.
OCD CPU clock output.
No connection.
No connection.
Direct switched capacitor block input.
Ground connection.
Ground connection.
External Analog Ground (AGND) input.
OCD high speed clock output.
J6 I/O
J7 I/O
J8 I/O M
J9 Power
J10 Power
K1 Power
K2 Power
K3
K4
K5 Power
K6 I/O
K7 I/O
K8 I/O
K9 Power
K10 Power
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
D-
Vdd
Ground connection.
Ground connection.
Supply voltage.
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
No connection.
Supply voltage.
Ground connection.
Ground connection.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.
Figure 7-6. CY8C24094 OCD (Not for Production)
1 2 3 4 5 6 7 8 9 10
A
Vss Vss NC NC NC Vdd NC NC Vss Vss
B
Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss
C
NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2] NC
D
NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] CClk
E
NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] HClk
F
ocde P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1]
G
ocdo P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]
H
NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]
J
Vss Vss D + D - Vdd P7[7] P7[0] P5[2] Vss Vss
K
Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss
BGA (Top View)
Document Number: 38-12018 Rev. *O
Page 14 of 47
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