CY7C68300C_09 Datasheet, PDF (14/41 Pages) Cypress Semiconductor – EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
DRVPWRVLD
When this pin is enabled with bit 0 of configuration address 0x08
(DRVPWRVLD Enable), the AT2LP informs the host that a
removable device, such as a CF card, is present. The AT2LP
uses DRVPWRVLD to detect that the removable device is
present. Pin polarity is controlled by bit 1 of configuration
address 0x08. When DRVPWRVLD is deasserted, the AT2LP
reports a “no media present” status (ASC = 0x3A, ASQ = 0x00)
when queried by the host. When the media has been detected
again, the AT2LP reports a “media changed” status to the host
(ASC = 0x28, ASQ = 0x00) when queried.
When a removable device is used, it is always considered by the
AT2LP to be the IDE master device. Only one removable device
may be attached to the AT2LP. If the system only contains a
removable device, bit 6 of configuration address 0x08 (Search
ATA Bus) must be set to ‘0’ to disable ATA device detection at
startup. If a non-removable device is connected in addition to a
removable media device, the non-removable device must be
configured as IDE slave (device address 1).
GPIO Pins
The GPIO pins enable a general purpose input and output
interface. There are several different interfaces to the GPIO pins:
■ Configuration bytes 0x09 and 0x0A contain the default settings
for the GPIO pins upon initial AT2LP configuration.
■ The host can modify the settings of the GPIO pins during
operation. This is done with vendor-specific commands
described in “Programming the EEPROM” on page 34.
■ The status of the GPIO pins is returned on the interrupt endpoint
(EP1) in response to a SYSIRQ. See “SYSIRQ” on page 13 for
SYSIRQ details.
LOWPWR#
LOWPWR# is an output pin that is driven to ‘0’ when the AT2LP
is not in suspend. LOWPWR# is placed in Hi-Z when the AT2LP
is in a suspend state. This pin only indicates the state of the
AT2LP and must not be used to determine the status of the USB
host because of variations in the behavior of different hosts.
ATA Interface Pins
The ATA Interface pins must be connected to the corresponding
pins on an IDE connector or mass storage device. To enable
sharing of the IDE bus with other master devices, the AT2LP can
place all ATA Interface Pins in a Hi-Z state whenever
VBUS_ATA_ENABLE is not asserted. Enabling this feature is
done by setting bit 4 of configuration address 0x08 to ‘1’.
Otherwise, the ATA bus is driven by the AT2LP to a default
inactive state whenever VBUS_ATA_ENABLE is not asserted.
Design practices for signal integrity as outlined in the
ATA/ATAPI-6 specification must be followed with systems that
utilize a ribbon cable interconnect between the AT2LP’s ATA
interface and the attached mass storage device, especially if
Ultra DMA Mode is used.
VBUS_ATA_ENABLE
VBUS_ATA_ENABLE is typically used to indicate to the AT2LP
that power is present on VBUS. This pin is polled by the AT2LP
at startup and then every 20 ms thereafter. If this pin is ‘0’, the
AT2LP releases the pull up on D+ as required by the USB speci-
fication.
Also, if bit 4 of configuration address 0x08 is ‘1’, the ATA interface
pins are placed in a Hi-Z state when VBUS_ATA_ENABLE is ‘0’.
If bit 4 of configuration address 0x08 is ‘0’, the ATA interface pins
are still driven when VBUS_ATA_ENABLE is ‘0’.
ATAPUEN
This output can be used to control the required host pull up
resistors on the ATA interface in a bus-powered design to
minimize unnecessary power consumption when the AT2LP is in
suspend. ATAPUEN is driven to ‘0’ when the ATA bus is inactive.
ATAPUEN is driven to ‘1’ when the ATA bus is active. ATAPUEN
is set to a Hi-Z state along with all other ATA interface pins if
VBUS_ATA_ENABLE is deasserted and the ATA_EN function-
ality (bit 4 of configuration address 0x08) is enabled (0).
ATAPUEN can also be configured as a GPIO input. See “HID
Functions for Button Controls” on page 15 for more information
on HID functionality.
PWR500#
The AT2LP asserts PWR500# to indicate that VBUS current may
be drawn up to the limit specified by the bMaxPower field of the
USB configuration descriptors. If the AT2LP enters a low-power
state, PWR500# is deasserted. When normal operation is
resumed, PWR500# is restored. The PWR500# pin must never
be used to control power sources for the AT2LP. In the 56-pin
package, PWR500# only functions during bus-powered
operation.
PWR500# can also be configured as a GPIO input. See “HID
Functions for Button Controls” on page 15 for more information
on HID functionality.
VBUSPWRD
VBUSPWRD is used to indicate self- or bus-powered operation.
Some designs require the ability to operate in either self- or
bus-powered modes. The VBUSPWRD input pin enables these
devices to switch between self-powered and bus-powered
modes by changing the contents of the bMaxPower field and the
self-powered bit in the reported configuration descriptors (see
Table 4).
Note that current USB host drivers do not poll the device for this
information, so the effect of this pin is only seen on a USB or
power on reset.
Table 4. Behavior of Descriptor Data that is Dependent Upon
VBUSPWRD State
Pin
bMaxPower
Reported
Value
bmAttributes
bit 6
Reported
Value
VBUSPWRD = ‘1’
0xFA
(500 mA)
‘0’
(bus-powered)
VBUSPWRD = ‘0’
VBUSPWRD
N/A (56-pin)
0x01
(2 mA)
The value
from configu-
ration
address 0x34
is used.
‘1’
(self-powered)
‘0’ if
bMaxPower >
0x01
‘1’ if
bMaxPower ≤
0x01
Document 001-05809 Rev. *C
Page 14 of 41
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