CY7C43663AV Datasheet, PDF (14/28 Pages) Cypress Semiconductor – 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

AC Test Loads and Waveforms (–10, –15)
3.3V
OUTPUT
R1 = 330Ω
C_L = 30 pF^[16]
R2 = 680Ω
INCLUDING
JIG AND
SCOPE
AC Test Loads and Waveforms (–7)
V_CC/2
50 Ω
I/O
Z0 = 50Ω
CY7C43663AV
CY7C43643AV
CY7C43683AV
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Switching Characteristics Over the Operating Range
CY7C43643/63/
83AV
–7
Parameter
Description
Min. Max.
f_S
t_CLK
t_CLKH
t_CLKL
t_DS
Clock Frequency, CLKA or CLKB
133
Clock Cycle Time, CLKA or CLKB
7.5
Pulse Duration, CLKA or CLKB HIGH
3.5
Pulse Duration, CLKA or CLKB LOW
3.5
Set-Up Time, A_0–35 before CLKA↑ and B_0–35 before
3
CLKB↑
t_ENS
Set-Up Time, CSA, W/RA, ENA, and MBA before
3
CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑
t_RSTS
Set-Up Time, MRS1/MRS2, PRS, RT LOW before
2.5
CLKA↑ or CLKB↑^[17]
t_FSS
Set-Up Time, FS0 and FS1 before MRS1/MRS2
5
HIGH
t_BES
t_SPMS
t_SDS
t_SENS
t_FWS
t_DH
Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH
5
Set-Up Time, SPM before MRS1/MRS2 HIGH
5
Set-Up Time, FS0/SD before CLKA↑
3
Set-Up Time, FS1/SEN before CLKA↑
3
Set-Up Time, FWFT before CLKA↑
0
Hold Time, A_0–35 after CLKA↑ and B_0–35 after
0
CLKB↑
t_ENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; 0
CSB, W/RB, ENB, and MBB after CLKB↑
Note:
16. C_L = 5 pF for t_DIS.
17. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
CY7C43643/
63/83AV
–10
Min. Max.
100
10
4
4
4
4
4
7
7
7
4
4
0
0
0
CY7C43643/
63/83AV
–15
Min. Max.
67
15
6
6
5
Unit
MHz
ns
ns
ns
ns
5
ns
5
ns
7.5
ns
7.5
ns
7.5
ns
5
ns
5
ns
0
ns
0
ns
0
ns
Document #: 38-06024 Rev. *C
Page 14 of 28