CY7C1561V18_08 Datasheet, PDF (14/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
The state diagram for the TAP controller follows. ^[12]
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
1
IDLE
SELECT
1
DR-SCAN
0
1
CAPTURE-DR
0
SHIFT-DR
0
1
1
EXIT1-DR
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
1
SELECT
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
0
1
1
EXIT1-IR
0
PAUSE-IR
0
1
0
EXIT2-IR
1
UPDATE-IR
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-05384 Rev. *F
Page 14 of 28
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