CY7C1480V25 Datasheet, PDF (14/32 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

CY7C1480V25
CY7C1482V25
CY7C1486V25
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
TAP Timing
1
2
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
3
4
5
6
Test Clock
(TCK)
Test Mode Select
(TMS)
t _TH
tTL
tTMSS tTMSH
t _CYC
t _TDIS
t _TDIH
Test Data-In
(TDI)
t _TDOV
Test Data-Out
(TDO)
t _TDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range^{[9, 10]}
Parameter
Description
Min
Clock
t_TCYC
TCK Clock Cycle Time
50
t_TF
TCK Clock Frequency
t_TH
TCK Clock HIGH time
20
t_TL
TCK Clock LOW time
20
Output Times
t_TDOV
TCK Clock LOW to TDO Valid
t_TDOX
TCK Clock LOW to TDO Invalid
0
Setup Times
t_TMSS
TMS Setup to TCK Clock Rise
5
t_TDIS
TDI Setup to TCK Clock Rise
5
t_CS
Capture Setup to TCK Rise
5
Hold Times
t_TMSH
TMS Hold after TCK Clock Rise
5
t_TDIH
TDI Hold after Clock Rise
5
t_CH
Capture Hold after Clock Rise
5
Notes
9. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. t_R/t_F = 1 ns.
Max
20
10
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05282 Rev. *H
Page 14 of 32
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