CY7C1292DV18_06 Datasheet, PDF (14/23 Pages) Cypress Semiconductor – 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture

CY7C1292DV18
CY7C1294DV18
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Value
CY7C1292DV18
CY7C1294DV18
000
000
11010011010010110
11010011010100110
00000110100
00000110100
1
1
Description
Version number.
Defines the type of SRAM.
Unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan Cells
Bit Size
3
1
32
107
Instruction Codes
Instruction
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Code
000
001
010
011
100
101
110
111
Description
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Document #: 001-00350 Rev. *A
Page 14 of 23
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