CY28346_05 Datasheet, PDF (14/20 Pages) Cypress Semiconductor – Clock Synthesizer with Differential CPU Outputs

CY28346
Maximum Ratings^[5]
Input Voltage Relative to V_SS:.............................. V_SS – 0.3V
Input Voltage Relative to V_DDQ or AV_DD: ............. V_DD + 0.3V
Current Accuracy^[6]
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:.................................... 0°C to +85°C
Maximum Power Supply:................................................ 3.5V
Parameter
Conditions
Iout
V_DD = nominal (3.30V)
Iout
V_DD = 3.30 ± 5%
Configuration
M0 = 0 or 1 and Rr (see Table 1)
All combinations of M0 or 1 and Rr
(see Table 1)
Load
Nominal test load for given
configuration
Nominal test load for given
configuration
Min.
–7%
Inom
–12%
Inom
Max.
+ 7%
Inom
+ 12%
Inom
DC Parameters (V_DD = V_DDA = 3.3V ±5%, TA = 0°C to +70°C)
Parameter
Description
Conditions
Min. Typ. Max. Unit
I_DD3.3V Dynamic Supply Current
All frequencies at maximum values^[7]
280 mA
I_PD3.3V Power-down Supply Current
PD# asserted
Note 8 mA
C_IN
Input Pin Capacitance
5
pF
C_OUT
Output Pin Capacitance
6
pF
L_PIN
Pin Inductance
7
nH
C_XTAL
Crystal Pin Capacitance
Measured from the X_IN or X_OUT pin to ground 30
36
42
pF
AC Parameters (V_DD = V_DDA = 3.3V ±5%, T_A = 0°C to +70°C)
66 MHz
100 MHz
133 MHz
200 MHz
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Crystal
T_DC
T_PERIOD
X_IN Duty Cycle
X_IN period
47.5 52.5
69.84 71.0
47.5 52.5 47.5 52.5 47.5 52.5
69.84 71.0 69.84 71.0 69.84 71.0
% 9, 10, 11
ns 9, 12,
13, 10
V_HIGH
V_LOW
T_R / T_F
T_CCJ
X_IN HIGH Voltage
0.7V_DD V_DD 0.7V_DD V_DD 0.7V_DD V_DD 0.7V_DD V_DD V
X_IN LOW Voltage
0 0.3V_DD 0 0.3V_DD 0 0.3V_DD 0 0.3V_DD V
X_IN Rise and Fall Times
10.0
10.0
10.0
10.0 ns
X_IN Cycle to Cycle Jitter
500
500
500
500 ps
14
12, 15,
10
CPU at 0.7V Timing
T_DC
CPUT and CPUC Duty 45
55
45
55
45
55
45
55 % 15, 16,
Cycle
19
T_PERIOD
CPUT and CPUC
Period
14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 15, 16,
19
T_SKEW
Any CPU to CPU Clock
100
Skew
100
100
100 ps 12, 15,
16
Notes:
5. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. Inom refers to the expected current based on the configuration of the device.
7. All outputs loaded as per maximum capacitive load table.
8. Absolute value = ((Programmed CPU Iref) × (2)) + 10 mA.
9. This parameter is measured as an average over 1 µs duration, with a crystal center frequency of 14.31818 MHz.
10. When Xin is driven from an external clock source.
11. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
12. All outputs loaded as perTable 9 below.
13. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
14. Measured between 0.2V_DD and 0.7V_DD.
15. This measurement is applicable with Spread ON or Spread OFF.
16. Measured at crossing point (Vx) or where subtraction of CLK–CLK# crosses 0V Measured from V_OL = 0.175V to V_OH = 0.525V.
17. Measured from V_OL = 0.175V to V_OH = 0.525V.
18. Determined as a fraction of 2*(Trise–Tfall)/ (Trise+Tfall).
19. Test load is Rta = 33.2Ω, Rd = 49.9Ω.
Document #: 38-07331 Rev. *C
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