CY14E256LA_12 Datasheet, PDF (14/19 Pages) Cypress Semiconductor – 256-Kbit (32 K × 8) nvSRAM

CY14E256LA
Hardware STORE Cycle
Over the Operating Range
Parameter
Description
t_DHSB
t_PHSB
t_SS ^{[34, 35]}
HSB to output active time when write latch not set
Hardware STORE pulse width
Soft sequence processing time
CY14E256LA
Min
Max
Unit
–
25
ns
15
–
ns
–
100
s
Switching Waveforms
Write Latch set
HSB (IN)
tPHSB
HSB (OUT)
tDELAY
Figure 11. Hardware STORE Cycle ^[36]
tSTORE
SO
RWI
tHHHD
tLZHSB
Write Latch not set
HSB (IN)
tPHSB
HSB (OUT)
tDELAY
tDHSB
tDHSB
HSB pin is driven high to V_CCQ only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
RWI
Figure 12. Soft Sequence Processing ^{[34, 35]}
Address
CE
V_CC
Soft Sequence
t_SS
Command
Address #1
t_SA
Address #6
t_CW
Soft Sequence
t_SS
Command
Address #1
Address #6
t_CW
Notes
34. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
35. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
36. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-54952 Rev. *I
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