W149 Datasheet, PDF (13/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W149
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 48 MHz (48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
t_R
Output Rise Edge
Measured from 0.4V to 2.4V
Rate
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabiliza- Assumes full supply voltage reached within 1 ms from
tion from Power-up power-up. Short cycles exist prior to frequency stabili-
(cold start)
zation.
Z_o
AC Output Impedance Average value during switching transition. Used for de-
termining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
48.008
+167
57/17
0.5
2
0.5
2
45
55
3
40
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 24 MHz (24.004 – 24)/24
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabiliza- Assumes full supply voltage reached within 1 ms from
tion from Power-up
power-up. Short cycles exist prior to frequency stabili-
(cold start)
zation.
Z_o
AC Output Impedance Average value during switching transition. Used for de-
termining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
24.004
+167
57/34
0.5
2
0.5
2
45
55
3
40
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
Ordering Information
Ordering Code
Package
Name
W149
H
Package Type
48-Pin SSOP (300-mil)
Document #: 38-00856-A
13