CYRF69103A-40LFXC Datasheet, PDF (13/68 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69103
11. CPU Registers
11.1 Flags Register
The Flags Register can only be set or reset with logical instruction.
Table 11-1. CPU Flags Register (CPU_F) [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
XIO
Super
Carry
Zero
Global IE
Read/Write
–
–
–
R/W
R
RW
RW
RW
Default
0
0
0
0
0
0
1
0
Bits 7:5 Reserved
Bit 4
XIO
Set by the user to select between the register banks.
0 = Bank 0
1 = Bank 1
Bit 3
Super
Indicates whether the CPU is executing user code or Supervisor Code (This code cannot be accessed directly by
the user).
0 = User Code
1 = Supervisor Code
Bit 2
Carry
Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation.
0 = No Carry
1 = Carry
Bit 1
Zero
Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation.
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0
Global IE
Determines whether all interrupts are enabled or disabled.
0 = Disabled
1 = Enabled
Note This register is readable with explicit address 0xF7. The OR F, expr and AND F, expr must be used to set and clear the
CPU_F bits.
11.2 Accumulator Register
Table 11-2. CPU Accumulator Register (CPU_A)
Bit #
7
6
5
4
3
2
1
0
Field
CPU Accumulator [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
Bits 7:0 CPU Accumulator [7:0]
8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode.
Document #: 001-07611 Rev *F
Page 13 of 68
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