CYII4SC014KAA-GTC Datasheet, PDF (13/27 Pages) Cypress Semiconductor – 14Megapixel CMOS Image Sensor

CYII4SC014KAA-GTC
CYII4SM014KAA-GEC
SPI Register
SPI Interface Architecture
The elementary unit cell of the serial to parallel interface consists of two D-flip-flops. The architecture is shown in Figure 13. 16
of these cells are connected in parallel, having a common /CS and SCLK form the entire uploadable parameter block, where D_in
is connected to D_out of the next cell. The uploaded settings are applied to the sensor on the rising edge of signal /CS.
Figure 13. SPI Interface
To sensor core
16 outputs to sensor core
D
Q
CS
C
Din
SCLK
D
Q
C
Unity Cell
Din
SCLK
Dout
Entire uploadable parameter block
CS
Dout
SCLK
Din
CS
Data
valid
Tsclk
D0
D1
D2
Th
D15
Ts
Table 6. Timing Requirements Serial-Parallel Interface
Parameter
Tsclk
Ts
Th
Value
100 ns
50 ns
50 ns
SPI Register Definition
Sensor parameters can be serially uploaded inside the sensor
at the start of a frame. The parameters are:
• Subsampling modes for X and Y shift registers (3-bit code
for 6 subsampling modes)
• Power control of the output amplifiers, column amps and
pixel array. Each amplifier can be individually powered
up/down
• Output crossbar switch control bits. The crossbar switch is
used to route the green pixels to the same output amplifiers
at all time. A first bit controls the crossbar. When a second
bit is set, the first bit will toggle on every CLK_Y edge in
order to automatically route the green pixels of the bayer
filter pattern.
The code is uploaded serially as a 16-bit word (LSB uploaded
first).
Table 7 on page 14 lists the register definition. The default
code for a full resolution readout is 33342 (decimal) or 1000
0010 0011 1110.
Document #: 38-05709 Rev. *B
Page 13 of 27
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