CYIFS731 Datasheet, PDF (13/20 Pages) Cypress Semiconductor – Reduces Systemic EMI

CYIFS731
Application Notes and Schematics
The schematic diagram shown below is a simple minimum component application example of an CYIFS731 design. In the case shown
below, the control lines are configured for the following parameters.
Figure 11. Simple minimum component application example of an CYIFS731 design ^[5]
CYIFS731
The circuit shown in Figure 12 is the equivalent oscillator circuit
used in the CYIFS731.
Figure 12. Equivalent oscillator circuit used in the CYIFS731
Calculating dB Reduction
The dB reduction for a give frequency and spread can be
calculated using a simple formula. This formula is only helpful in
determining a relative dB reduction for a given application. This
formula assumes an ideal clock with 50% duty cycle and
therefore only predicts the EMI reduction of odd harmonics.
Other circumstances such as non-ideal clock and noise will affect
the actual dB reduction. The formula is as follows;
dB = 6.5 + 9(Log10(F)) + 9(Log10(P))
Where; F = Frequency in MHz, P = total % spread (2.5% = 0.025)
Using a 50 MHz clock with a 2.5% spread, the theoretical dB
reduction would be;
dB @ 50 MHz (Fund) = 6.5 + 15.29 – 14.42 = 7.37
dB @ 150 MHz (3^rd) = 6.5 + 19.58 – 14.42 = 11.66
dB @ 550 MHz (11^th) = 6.5 + 24.66 – 14.42 = 16.74
Note
5. C3 and C4 values assume a first order crystal with C_L = 18 pF.
Document Number: 001-73426 Rev. *D
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