CYBL10X6X Datasheet, PDF (13/42 Pages) Cypress Semiconductor – Programmable Radio-on-Chip With Bluetooth Low Energy (PRoC BLE)

PRoC BLE: CYBL10X6X
Family Datasheet
Power
PRoC BLE can be supplied from batteries with a voltage range
of 1.9 V to 5.5 V by directly connecting to the digital supply
(V_DDD), analog supply (V_DDA), and radio supply (V_DDR) pins. The
internal LDOs in the device regulate the supply voltage to
required levels for different blocks. The device has one regulator
for the digital circuitry and separate regulators for radio circuitry
for noise isolation. The analog circuits run directly from the
analog supply (V_DDA) input. The device uses separate regulators
for Deep Sleep and Hibernate modes to minimize the power
consumption. The radio stops working below 1.9 V, but the rest
of the system continues to function down to 1.71 V without RF.
Note that V_DDR must be supplied whenever V_DDD is supplied.
Bypass capacitors must be used from VDDx (x = A, D, or R) to
ground. The typical practice for systems in this frequency range
is to use a capacitor in the 1-µF range in parallel with a smaller
capacitor (for example, 0.1 µF). Note that these are simply rules
of thumb and that, for critical applications, the PCB layout, lead
inductance, and the bypass capacitor parasitic should be
simulated to design to obtain optimal bypassing.
Power Supply
V_DDD
V_DDA
V_DDR
V_CCD
Bypass Capacitors
0.1-µF ceramic at each pin plus bulk
capacitor 1 µF to 10 µF
0.1-µF ceramic at each pin plus bulk
capacitor 1 µF to 10 µF
0.1-µF ceramic at each pin plus bulk
capacitor 1 µF to 10 µF
1-µF ceramic capacitor at the VCCD pin
V_REF (optional) The internal bandgap may be bypassed
with a 1-µF to 10-µF capacitor
Low-Power Modes
PRoC BLE supports five power modes. Refer to Table 5 for more
details on the system status. The PRoC BLE device consumes
the lowest current in Stop mode; the device wakeup from stop
mode is with a system reset through the XRES or WAKEUP pin.
It can retain the SRAM data in Hibernate mode and is capable of
retaining the complete system status in Deep-Sleep mode.
Table 5 shows the different power modes and the peripherals
that are active.
Table 5. Power Modes System Status
Power Mode
Active
Sleep
Current
Consumption
850 µA + 260 µA
per MHz^[1]
1.1 mA at 3 MHz
Code
Execution
Yes
No
Deep Sleep
1.3 μA
No
Hibernate
150 nA
No
Stop
60 nA
No
Digital
Peripherals
Available
All
All
WDT, LCD,
I²C/SPI,
Link-Layer
No
No
Analog
Peripherals
Available
All
All
POR, BOD
POR, BOD
No
Clock
Sources
Available
All
Wake Up
Sources
–
Wake-Up
Time
–
All
WCO,
ILO
No
No
Any interrupt
source
GPIO, WDT,
I²C/SPI Link
Layer
GPIO
Wake-Up pin,
XRES
0
25 μs
2 ms
2 ms
Note
1. For CPU subsystem.
Document Number: 001-90478 Rev. *K
Page 13 of 42