CY8C9520 Datasheet, PDF (13/25 Pages) Cypress Semiconductor – 20-, 40-, and 60-Bit I/O Expander with EEPROM

CY8C95xx Preliminary Data Sheet
3. Register Reference
3.2.9 Drive Mode Registers (1Dh-23h)
Each port's data pins can be set separately to one of seven
available modes: pull-up/-down, open drain high/low, strong
drive fast/slow, or high-impedance input. To perform this config-
uration, the seven drive mode registers are used for the GPort
selected by the Port Select register (18h). Each ’1’ written to
this register changes the corresponding line drive mode. Regis-
ters 1Dh through 23h have last-register priority meaning that
the bit set to high in which the last register was written will over-
ride those that came before. Reading these registers reflects
the actual setting, not what was originally written.
Table 3-4. Drive Mode Register Settings
Register
1Dh
1Eh
1Fh
20h
21h
22h
23h
Pin State
Resistive pull up
Resistive pull down
Open drain high
Open drain low
Strong drive
Slow strong drive
HIgh impedance
Description
Resistive high, strong low (default)
Strong high, resistive low
Slow strong high, High-Z low
Slow strong low, High-Z high
Strong high, strong low, fast output mode
Strong high, strong low, slow output mode
High-Z
3.2.10 PWM Select Register (28h)
This register is used to select the PWM to be configured. Write
a value of 00h-0Fh to this register to select the PWM to pro-
gram with the following registers, 29h-2Bh.
3.2.11 Config (29h)
This register is used to choose the clock source for the PWM
selected by the PWM Select register (28h) and interrupt logic.
There are six available clock sources: 32 kHz (default), 24 MHz,
1.5 MHz, 93.75 kHz, 367.6 Hz, or previous PWM output. The
367.6 Hz clock is user programmable. It divides the 93.75 kHz
clock source by the divisor stored in the Divider register (2Ch).
The default divide ratio is 255. (see Table 3-5 for details). By
default, all PWMs are clocked from 32 kHz.
Table 3-5. PWM Clock Sources
Config PWM
xxxxx000b
xxxxx001b
xxxxx010b
xxxxx011b
xxxxx100b
xxxxx101b
PWM Clock Source
32 kHz (default)
24 MHz
1.5 MHz
93.75 kHz
367.6 Hz (programmable)
Previous PWM
Each PWM can generate an interrupt at the rising or falling
edge of the output pulse. There is a limitation on the clock
source for a PWM to generate an interrupt. Only the slowest
speed source (programmed to 367.6 Hz) with the divider equal
to 255 allows interrupt generation. Consequently, to create a
PWM interrupt, it is necessary to choose the programmable
divider output as the clock source (write xxxxx100b to Config
register (29h)), write 255 to the Divide register (2Ch), and select
PWM for pin output (1Ah).
Interrupt status is reflected in the Interrupt Status registers (10h-
17h) and can cause INT line activation if enabled by the corre-
sponding mask bit in the Interrupt Mask register:
3.2.12 Period Register (2Ah)
Table 3-6. Period Register
Config PWM
xxxx0xxxb
xxxx1xxxb
PWM Interrupt on
Falling pulse edge (default)
Rising pulse edge
This register sets the period of the PWM counter. Allowed val-
ues are between 1 and FFh. The effective output waveform
period of the PWM is:
t_OUT = Period ⋅ t_CLK
3.2.13 Pulse Width Register (2Bh)
This register sets the pulse width of the PWM output. Allowed
values are between zero and the (Period - 1) value. The duty
cycle ratio can be computed using the following equation:
DutyCycle = ^PulseWidth .
Period
3.2.14 Divider Register (2Ch)
This register sets the frequency on the output of the program-
mable divider:
Frequency = ^{93.75 kHz} .
Divider
Allowed values are between 1 and 255.
3.2.15 Enable Register (2Dh)
The WDE bit configures the write disable pin to operate either
as a GPIO or as WD. It also enables/disables EEPROM opera-
tions (EEE bit) or makes the EEPROM read-only (EERO bit).
Bit assignments are shown in Table 3-7 on page 14.
August 17, 2005
Document No. 38-12036 Rev. *A
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